Usman Mughal

Founder, Patent Attorney, Shareholder

U@mgf.law

Phone 971-634-0286 (main)

Cell 503-327-5614 (cell)

Education Details

B.S. Computer Engineering, Summa Cum Laude
North Carolina State University, Raleigh, NC

M.S. Electrical Engineering, Thesis
North Carolina State University, Raleigh, NC

J.D. Intellectual Property Law, Cum Laude, Lewis & Clark Law Review
Lewis & Clark Law School, Portland, OR

Admissions

U.S Patent and Trademark Office
Oregon

Assistant

Katherine Campbell
katherine@mgf.law

Biography

Usman has been working in the patent preparation and prosecution field since 2008. He has a B.S. degree in computer engineering and a M.S. degree in electrical engineering. Usman defended his M.S. thesis from NC State University on hierarchical approach to global modeling of active antenna arrays. Usman went on to join Intel Corp. where he worked as an analog/mixed-signal design engineer for 9 years. Usman designed PLLs, DLLs, I/Os, thermal sensors, memory circuits, voltage regulators, debug software, clock distribution circuits, etc. At Intel, Usman received awards for his work and was an inventor on 11 patents.

While working at Intel, Usman attended law school because of his interest in becoming a patent attorney. After passing the bar, Usman worked in law firms as an associate and then as a named partner. He co-managed day-to-day domestic and foreign prosecution and budgeting activities for a former client’s power management and circuits patent portfolio for various law firms. Usman’s technology practice for patents is deep and broad and covers 5G RAN standard, mixed signal circuits, antennas, software, memories (volatile and non-volatile), semiconductor process and packaging, business methods, artificial intelligence hardware, and processors.

Usman is regularly recognized for his work. For example, Usman is listed as a “Rising star” by the Oregon Super Lawyers over multiple years. He is rated as “Top Lawyer” by Portland Monthly magazine. Usman is also active in the legal community and community at large. He is part of the founding board of Oregon Muslim Bar Association (OMBA). At OMBA, he interviews judicial and political candidates for endorsement requests. Usman also co-founded a free health clinic in Portland, Oregon, which was later merged with a larger free health provider. Usman supports education for the underprivileged. He led the funding and construction of a primary school in a remote village of Pakistan. Over 50% of the student body is female in that school.

Patents

I/O Circuit Patents:

“Apparatus and Method for Dynamic On-Die Termination in an Open-Drain Bus Architecture System,” Inventors: Usman A. Mughal, Razi Uddin, Chee How Lim et al. Patent#: 6,411,122 Issued: 06/25/2002.

This Method Saved Up To 50% Of Dynamic Power At The Driver Side Of AGTL Buffer. It Was The First Time Intel Used This Novel Technique To Save Power For Mobile CPUs While Preserving Signal Integrity Of The Bus.

“Apparatus and Method to Provide a Single Reference Component for Multiple Circuit Compensation using Digital Impedance Code Shifting,” Inventors: Usman A. Mughal, et al, Patent#: 6,545,522, Issued: 04/08/2003.

This Method Used A Single Package Pin As Reference For Termination Resistance, I/O Slew Rate, And Pull-Down Resistance Compensation. It Saved Intel Millions Of Dollars Of Package Pin Cost.

“Apparatus and Method to use a Single Reference Component in a Master-Slave Configuration for Multiple Circuit Compensation,” Inventors: Usman A, Mughal, Gregory Taylor, et al, Patent#: 6,535,047, Issued: 03/18/2003.

This Method Used A Single Package Pin As Reference For Compensating Many Circuits. The Circuit Technique Used A Master-Slave Configuration. It Saved Intel Millions Of Dollars Of Package Pin Cost.

“Circuit Compensation Technique,” Inventors: C.H. Lim and Usman A. Mughal, Patent#: 6,509,780, Issued: 01/21/2003.

An Intelligent Compensation Scheme That Minimized Glitches In The Actual Circuits That Used Compensation Information. By Removing These Glitches, Timing Margin On The I/O Improved Thus Allowing Them To Run Faster.

“Apparatus and Method for Linear On-Die Termination in an Open Drain Bus Architecture System,” Inventors: Raghu Raman, Usman A. Mughal, et al, Patent#: 6,424,170, Issued: 07/23/2002.

A Novel Termination Circuit For I/Os That Provided Linear Resistance In The Operating Range Of 45-65 Ohms. The Design Also Protected Transistor Oxide, Thus Its Longevity, By Reducing Stress Across Gate-Drain Voltages.

Using A Single Package Pin As Reference For Termination Resistance, Multiple I/O Driver Circuits Were Compensated By Using One Compensated Circuit As Reference. Saved Intel Millions Of Dollars Of Package Pin Cost.

By Shifting Compensation Codes, Impedances Were Changed For Different I/O Terminations. The Method Used The Same Reference Resistor For Uni-Processor And Dual-Processor I/O Termination Resistance. Saved Intel Money.

Platform Patent:

“Bus Termination Scheme for Flexible Uni-Processor and Dual Processor Platforms,” Inventors: V. Ramachandran, Usman A. Mughal, and Chee How Lim, Patent#: 6,522,165, Issued: 02/18/2003.

A Novel Termination Scheme Using A Single Platform Topology For Uni And Dual-Processor Systems Thus Saving An Extra Motherboard Design. The Design Preserved System Signal Integrity Of A Uni-Processor System.

PLL and DLL Circuit Patents:

“Variable Lock Window for a Phase Locked Loop,” Inventors: K. L. Wong, Usman A. Mughal, et al. Patent#: 6,614,317 Issued: 09/02/2003.

Solved The Problem Of Losing PLL Lock Signal At Low Operating Frequencies When Jitter Can Be Higher. The Circuit Generated A Wide Lock Window At Low Frequency And A Narrow Lock Window At High Frequency.

“Variable Slope Adjustment Circuit for Digital Interpolators,” Inventors: Usman A. Mughal and Keng L. Wong. Patent#: 7,154,320: Issued: 12/27/2006.

A Novel Circuit Design Technique To Improve Operation Of Digital Phase Blenders. The Circuit Adjusted The Input Slopes To The Phase Blender To Generate Uniformly Spaced Interpolated Output Signals. Vital For DLLs.

Thermal Management Circuit Patent:

“Accurate on-die temperature measurement using remote sensing,” Inventors: David Duarte, Usman A. Mughal, et al., Patent#: 7,512,514: Issued: 03/31/2009.

Remote Thermal Sensing Technique That Improves Sensing Accuracy By Calibrating Errors Generated By Self-Heating Of The Silicon. Vital For Power Management Systems On CPUs.

Publications

External: IEEE – AP, MTT, EPEP, CICC; MURI, ITC, ISTFA, EDFAS, ISLPED:

Microwave – CAD:

Abdulla, M.N., Mughal, U.A., Steer, M.B., “Network characterization of a finite array of folded-slot antennas for spatial power combining application,” Antennas and Propagation Society, 1999. IEEE International Symp. 1999, Vol. 4, 1999.

Abdulla, M.N., Mughal, U.A., H.S. Tsai, Steer, M.B, et al., “A full-wave system simulation of a folded-slot spatial power combining amplifier array,” Microwave Symposium Digest, 1999 IEEE MTT-S International, Vol. 2, 1999.

Steer, M.B., Harvey, J.F., Mink, J.W, Mughal, U.A., et al, “Global modeling of spatially distributed microwave and millimeter-wave systems,” Microwave Theory and Techniques, IEEE Transactions, Vol. 47 Issue: 6 Part: 2, June 1999.

Mughal, U.A., “Hierarchical approach to global modeling of active antenna arrays,” M.S. Thesis North Carolina State University, 1999.

Christoffersen, C.E., Mughal, U.A., and Steer, M.B, “Object oriented microwave circuit simulator,” Int. J. on RF and Microwave Computer Aided Engineering, Vol. 10, Issue 3, 2000, pp. 164–182. (MURI).

Mixed Signal Circuit Validation:

Y. C. Pan, U. A. Mughal, et al, “Mixed signal validation of the Intel Pentium 4 microprocessor power-up sequence,” Proc. IEEE 12th Topical Meeting on EPEP, Princeton, NJ, pp. 163-166, Oct. 2003.

Analog Circuit Design:

B. Mauck, V. Ravichandran, and U. Mughal, “A Design-for-Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis,” International Test Conference (ITC) 2004.

B. M. Mauck, V. Ravichandran, and U. A. Mughal, “On-Die Parametric Analysis of SRAM,” 30^th International Symposium for Testing and Failure Analysis (ISTFA), 2004.

B. Mauck, V. Ravichandran, and U. Mughal, “On-Die LYA,” Electronic Device Failure Analysis Society (EDFAS), Vol. 9 No. 3, pp. 22-29, 2005.

D. Duarte, U. Mughal, et al, “Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007.

D. Duarte, U. Mughal, et al, “Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor,” International Symposium on Low Power Electronics and Design (ISLPED) 2007.

Internal: Intel DTTC:

Mixed Signal Circuit Validation:

Y.C. Pan, S. Kim, Usman A. Mughal, et al, “Mixed Signal Validation of Prescott Microprocessor Power-Up Sequence”, Intel Design and Test Technology Conference (DTTC), 2003.

Y. Pan, R. Cohen, U. Mughal, et al, “Analog Mixed Signal Validation of Special Circuits in Cedar Mill Microprocessor,” Special Validation Topics, Intel Design and Test Technology Conference (DTTC), 2004.

Analog Circuit Design:

B. Mauck, V. Ravichandran, and U. Mughal, “A Design for Test Technique for Parametric Analysis of SRAM: On-die LYA,” Memory and IO DFT, Intel Design and Test Technology Conference (DTTC), 2004.

D. Duarte, G. Geannopoulos, U. Mughal, and K. Wong, “Novel P1264 Thermal Sensor with Linearity and Range Compensation,” Intel Design and Test Technology Conference (DTTC), 2005.

D. Duarte, G. Geannopoulos, U. Mughal, C. Deng, and K. Wong, “Novel Circuits and Test Techniques for High Accuracy HVM Thermal Sensor Designs,” Intel Design and Test Technology Conference (DTTC), 2006.