Uday Shah

Patent Engineer

Email Uday@mgf.law

Phone 503-969-3594 (Cell)

Education Details

PhD. Engineering Science
Rensselaer Polytechnic Institute, Troy, NY
B.S. Physics
University of Oregon, Eugene, OR
J.D.
Lewis and Clark Law School, Portland, OR

Assistant

Katherine Campbell
katherine@impactpatents.com

Biography

Uday is a patent engineer with the firm and holds a J.D from Lewis and Clark Law School.

Prior to joining Mughal IP, Uday worked as a plasma etch engineer and as an integration engineer in Components Research at Intel Corporation for over 14 years. While at components research, Uday focused on developing novel plasma etch solutions for a wide variety of programs in the areas of transistors (Hi-K metal gate, Tri-Gate, silicon nanowire, III-V and Ge), memory (E-DRAM, Magnetic Tunnel Junction, Floating Body Cell), EUV lithography and directed self-assembly. Uday’s integration work focused on developing novel memory devices (Magnetic Tunnel Junction and Resistive Random Access Memory).

Uday holds a PhD in engineering science from Rensselaer Polytechnic Institute, Troy, New York, with a focus on high temperature plasma diagnostics.

Uday holds over 100 US Patents in the areas of Hi-K metal gate transistors, TriGate transistors, Germanium transistors, III-V transistors, nanowire transistors, optical interconnects, EDRAM memory, magnetic memory, resistive random access memory (RRAM) and floating body cell memory.

Uday was awarded an Intel Achievement Award for Tri-Gate Transistor Innovation (Highest Technical Award at Intel), and nine Divisional awards for contributions to Planar/Non-Planar Transistor and Memory research. Uday was also recognized at the Smithsonian Museum’s American Enterprise Exhibit for Intel’s Tri-Gate Innovation (July 2015).

Patents

https://patents.google.com/?assignee=Uday+Shah&inventor=uday+shah

Publications

External: – PESM, AVS, IEDM, SPIE, VLSI, DPS:

Etch Challenges in Directed Self Assembly (Talk) PESM Mechelen, Belgium May 2011

III-V Etch Challenges for beyond 22nm node (Talk) AVS October 2010

Invited Talk on Challenges of III-V technology for logic applications DPS 2011 (could not attend)

Plasma Etch Challenges in Tri-Gate Device Fabrication (Talk) AVS October 2006

Electrostatics improvement in 3-D Tri-Gate over ultra-thin body planar InGaAs quantum well field effect transistors with High-K gate dielectric and scaled gate-to-drain/gate-to-source separation IEDM 2011 (co-author)

EUV Lithography for 22nm Half Pitch and Beyond: Exploring Resist Resolution, LWR, and Sensitivity Tradeoffs SPIE 2011 (co-author)

Silicon on Replacement Insulator Floating Body Cell Memory 2010 Symposium on VLSI Technology (co-author)

Non-Planar, Multi-Gate InGaAs Quantum Well Field Effect Transistors with High-K Gate Dielectric and Ultra-Scaled Gate-to-Drain/Gate-to-Source Separation for Low Power Logic Applications IEDM 2010 (co-author)

High Mobility Strained Germanium Quantum Well Field Effect Transistor as the P-Channel Device Option for Low Power (Vcc = 0.5 V) III-V CMOS Architecture IEDM 2010 (co-author)

EUV Lithography for 22nm Half Pitch and Beyond: Exploring Resist Resolution, LWR, and Sensitivity Tradeoffs 2010 International Symposium on EUV Lithography (co-author)

Advanced High-K Gate Dielectric for Short-Channel In0.7Ga0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Application IEDM 2009 (co-author)

Improvement in Line Width Roughness (LWR) by Post-Processing – SPIE 2008 (co-author)

Floating Body Cell with Independently-Controlled Double Gates for High Density Memory IEDM 2006 (co-author)

Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering Symposium on VLSI Technology 2006 (co-author)